Along with diversification of energy resources, power generation through use of a solar photovoltaic panel has become widespread as a type of renewable energy. Against the backdrop of lack of energy sources and reduction in CO2 emission in recent years, large-scale solar photovoltaic power generation plants, each of which exceeds 1000 kW and is called mega solar, have been actively built. Hereinafter, solar power generation is also called PV (Photo-Voltaic), and a solar photovoltaic panel (or solar panel) used therefor is also called a PV panel.
Output of a PV panel varies according to the amount of irradiation light. In particular, when the amount of light is small, such as at dawn, the output is small and the internal impedance is high. Connection of a load in a state with a high internal impedance reduces the voltage, which prevents normal operation as a power source, and the power source becomes an unstable power source. Control for stable operation even in a state where a PV panel receives a low amount of light is required. Such control is called optimization. Optimization means (circuit) is called an optimizer.
FIG. 6 is a circuit diagram illustrating a basic configuration of a conventional PV optimizer. FIG. 7 is an operation waveform diagram showing the level of gate signal of switching transistors constituting the circuit of FIG. 6. In FIG. 6, the “+” output and “−” output of the PV panel (not shown) are input into a PV input 101 (IN+) and a PV input 102 (IN−) of an optimizer 100: ground. Reference signs Q1, Q2, Q3, Q4 and Q5 denote first, second, third, fourth and fifth switching transistors, respectively. MOSFETs for N-channel power are adopted therefor. The enhancement type shown in the diagram is preferable for this circuit. However, the type is not necessarily limited thereto. Any type having similar functions may be adopted instead. Reference sign L1 denotes an inductance that has one end a connected to the PV input 101, and another end b connected to the drain terminals of the first switching transistor Q1, the second switching transistor Q2 and the fourth switching transistor Q4.
Reference sign T1 denotes a transformer that has one terminal a of primary winding (on the primary side) connected to the source electrode of the second switching transistor Q2 and the drain electrode of the third switching transistor Q3, and another electrode b connected to the source electrode of the fourth switching transistor Q4 and the drain electrode of the fifth switching transistor Q5. An end c of secondary winding (on the secondary side) of the transformer T1 that has the same polarity as that of the end a on the primary side is connected to the anode of a first diode D1 and the cathode of a second diode D2. Another end d is connected to a series connection point between a first capacitor C1 and a second capacitor C2, which are connected in series. The free end of the first capacitor C1 is connected to the cathode of the first diode D1 and one output 104 (OUT+) between the optimizer outputs. The free end of the second capacitor C2 is connected to the anode of the second diode D2 and the other output 105 (OUT−) between the optimizer outputs.
The source of the first switching transistor Q1, the source of the third switching transistor Q3, and the source of the fifth switching transistor Q5 are connected to the ground. The second transistor Q2 and the fourth switching transistor Q4 constitute a high-side switch. The third switching transistor Q3 and the fifth switching transistor Q5 constitute a low-side switch.
During normal operation of the PV optimizer 100 shown in FIG. 6, the gate signals Q1-G, Q2-G, Q3-G, Q4-G and Q5-G of the first switching transistor Q1, the second switching transistor Q2, the third switching transistor Q3, the fourth switching transistor Q4 and the fifth switching transistor Q5 are as shown in FIG. 7. Means for generating the gate signals Q1-G, Q2-G, Q3-G, Q4-G and Q5-G of the first to fifth switching transistors Q1 to Q5 is described later. The PV optimizer 100 is a bridge type step-up and voltage doubler rectification circuit. In FIG. 7, the switching frequency is, for example, 50 kHz. The first half of one period T is A, and the latter half is B. When the gate signal G in the first or latter half is at a high level (H), the corresponding transistor is ON. When the signal is at a low level (L), this transistor is OFF.
In the normal operation state, in the first half A of the period T, in an Aa interval, all the first to fifth switching transistors Q1 to Q5 are ON to excite the inductance L1; in an Ab interval, the first switching transistor Q1, the third switching transistor Q3 and the fourth switching transistor Q4 are turned OFF to thereby turn on the second switching transistor Q2 and the fifth switching transistor Q5. Consequently, the end a on the primary side of the transformer T1 is positive (+) and the other end b is ground (GND), thereby exciting the transformer T1 in the direction from the one end a to the other end b.
Upon entering the latter half B of one period, all the first to fifth switching transistors Q1 to Q5 are turned on to excite the inductance L1. Upon entering a Bb interval, the first switching transistor Q1, the second switching transistor Q2 and the fifth switching transistor Q5 are turned off to turn on only the third switching transistor Q3 and the fourth switching transistor Q4, thereby making the other end b on the primary side of the transformer T1 be positive (+) and making the one end a on the primary side of the transformer T1 be the ground (GND) to excite the transformer T1 in the direction from the other end b to the one end a, which is opposite to the above case.
The operation of one period of the switching frequency is thus finished, and the operation thereafter is its repetition. As with the primary side, the secondary side of the transformer T1 repeats the positive (+) and negative (−) polarities every half a period (T/2) of the switching frequency, and a voltage stepped up twice as high as the secondary-side voltage of the transformer T1 is obtained through the voltage doubler rectification by the first diode D1, the second diode D2, the first capacitor C1 and the second capacitor C2. The first switching transistor Q1 is not necessarily included. However, provision of this transistor can reduce the ON resistance while the second switching transistor Q2 to the fifth switching transistor Q5 are ON and, in turn, reduce the load.
During the normal operation, the operation is performed according to the gate signals shown in FIG. 7, and PWM control that changes the pulse width in the Aa interval in the first half A and the Ba interval of the latter half B in the switching period, and PFM control that changes time in the first half A and the latter half B in the switching period T, i.e., the period, are performed.
Disclosure of such types of conventional arts includes Patent Literature 1, Patent Literature 2 and Patent Literature 3.